The present invention relates to an input/output buffer design capable of handling multiple types of signals. More particularly, the present invention relates to an output buffer capable of driving loads for different types of circuitry, such as Peripheral Component Interconnect (PCI) circuitry, Gunnings Transceiver Logic (GTL), Emitter Coupled Logic (ECL), Series Stub Terminated Logic (SSTL), or Pseudo Emitter Coupled Logic (PECL) to desired output levels.
Circuits constructed in accordance with standards such as PCI, GTL, ECL, SSTL or PECL each have different high and low state characteristics. Although some of the states for different circuit types will have similar voltage and current requirements, others will be different.
PCI provides a high speed bus interface for PC peripheral I/O and memory and its input and output voltage and current requirements are similar to CMOS. For instance, the high and low voltage states will vary from rail to rail (VDD to VSS), with high impedance low current inputs and outputs.
GTL provides a lower impedance higher current high state, providing a low capacitance output to provide higher speed operation. The transition region for GTL is significantly smaller than for CMOS.
PECL provides a high current low voltage to provide a smaller transition region compared to CMOS to better simulate emitter coupled logic (ECL). The PECL offers a low impedance outputs and a high impedance inputs to be the most suitable choice of logic to drive transmission lines to minimize reflections.
Integrated circuit chips, such as a field programmable gate array (FPGA) chip, or a complex programmable logic device (CPLD), provide functions which may be used in a circuit with components operating with any of the logic types, such as PCI, GTL, ECL, PECL, or SSTL described above. It would be desirable to have an input/output buffer for use on a general applicability chip such as a FPGA or CPLD to selectively make the chip compatible with any of these logic types.
In accordance with the present invention, an input/output buffer circuit includes an output buffer which can selectively be made compatible with any of a number of logic types, such as PCI, GTL, or PECL, as well as any output voltage level such as 1.8V or 3.3V.
In accordance with the present invention, the output buffer portion of the circuit includes an input signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). The output buffer includes circuitry provides necessary drive current to transition a load at a desired rate and to set output voltage limits, while limiting drive current after switching to enable a subsequent rapid output transition.
The output buffer portion includes pull up PMOS transistors with source-drain paths connecting VDD to the PAD, and NMOS pull down transistors with source-drain paths connecting VSS to drive the (PAD). The gates of the pull-up and pull down transistors and are driven by switching circuits to control the current and voltage levels of the pad during and after a transition of the input (D). Enable signals (PUENB1, PUENB2, PDENB1, PDENB2 and PDENB3) allow selective enabling of circuits driving one or more of either the pull-up transistors and the pull-down transistors to selectively control current driving the pad.
Pull-up switching circuitry receives a reference VRFNPU to accurately control current provided to the gate of one of the pull up transistor during transition of the output, while a reference VRFPU controls current provided to the gate of a pull up transistor after transition using a more limited current to clamp the output voltage to a desired value. Similarly, pulldown switching circuitry receives references VRFPD and VRFPPD to control current and limit voltage provided from the pull down transistor.
The circuits providing references VRFPU, VRFNPU, VRFPD and VRFPPD include components replicating the components of the pull-up and pull-down switching circuitry with feedback to accurately control current and voltage on the output. A number of the circuits providing the references are provided, and are configured to be selectively connected to the pull-up and pulldown circuits depending on the desired output voltage level.
The signal from the PAD is fed back through an input buffer circuit which can be programmably set to operate in one of a GTL, PECL, or PCI operation modes to provide a signal to a control node (INB). The control node (INB), then, provides a signal to enable the output buffer to rapidly transition the PAD, and to prepare for subsequent transitions of the PAD after another transition of the input D. Similarly, a slew rate control signal SLEW is provided to programmably control current from switching circuitry.